New methods for achieving faster transistors are being developed for the 90 nm semiconductor logic technology and below. One method for achieving faster transistors is to “strain” the silicon under the gate electrode. There are several ways to achieve the strain. One way is to etch away the silicon in the vicinity of the gate and to fill the recess with silicon germanium (SiGe) or another suitable material. The SiGe then forms a compressive strain on the gate channel. This compressive strain has been known to enhance hole mobility and thus improve the performance of PMOS devices.
FIG. 1 shows an example prior art PMOS transistor architecture that features a recess for forming the compressive strain. PMOS transistor 100 includes a polysilicon (or another suitable gate material) gate 108 that is surrounded by a spacer (102 of FIG. 1). A hard mask 118 is shown disposed above the polysilicon line. The spacer material may be formed of, for example, silicon nitride, which may be deposited by a low pressure chemical vapor deposition (LPCVD) process. An oxide liner may also be employed (not shown).
An etch process removes the silicon material (e.g., bulk c-Si or Silicon-On-Insulator, also known as SOI) in silicon layer 110 to a depth 104. The etching proceeds both vertically into silicon layer 110 and laterally under spacer 102 to form a recess 114, where the SiGe strain will be formed. Etching laterally under spacer 102 permits the strain to be formed near the gate channel, thereby improving performance.
Plasma etching has been employed for the silicon etch to create the strain recess. Due to shadowing of the neutrals species by the spacer (102) itself, for example, etching of the recess under the spacer (102) can be challenging. In particular, it is important that the etching of the strain recess be well controlled so that while a substantial and controlled amount of lateral etching of the silicon material into the region under spacer 102 is achieved, the remainder of silicon layer 110 is not unduly damaged. A well-controlled low V:L ratio etch (i.e., an etch into the silicon layer with a low vertical to lateral etch ratio) is therefore desired to effectively strain the gate and enhance hole mobility to improve device performance.